Senior Backend Java Engineer with Devops experience Shift Timings: USA, PST (Pacific Standard Time) Location: Remote (Brazil). Contract Were seeking a seasoned Backend Java Engineer who can own services end-to-end, from development through production infrastructure management. What
About us: Smarter Contact is the market-leading AI-powered text and voice communications platform for real estate professionals in the US market. Were building a best-in-class product with world-class talent to serve customers who rave about us.
Advanced english Design, simulate, implement and test digital logic for FPGA using Verilog Perform synthesis, timing analysis, floorplanning and test using Xilinx Vivado and Synopsys HAPS tools. Write constraints to fix timing problems. Programming skills in TCL (for
Advanced english Design, simulate, implement and test digital logic for FPGA using Verilog Perform synthesis, timing analysis, floorplanning and test using Xilinx Vivado and Synopsys HAPS tools. Write constraints to fix timing problems. Programming skills in TCL (for
Já pensou em fazer parte de uma das maiores e mais respeitadas redes de franquias do Grupo Boticário? Chegou a sua chance! A Gentil Negócios , com 40 anos de excelência no mercado, está em busca
Advanced english Design, simulate, implement and test digital logic for FPGA using Verilog Perform synthesis, timing analysis, floorplanning and test using Xilinx Vivado and Synopsys HAPS tools. Write constraints to fix timing problems. Programming skills in TCL (for
Were looking for a direct response video editor who can produce 1-3 performance ads per day — consistently, quickly, and without hand-holding. Youll receive reference ads, raw footage, AI-generated visuals, voiceover audio, product photography, UGC clips,
About us: Smarter Contact is the market-leading AI-powered text and voice communications platform for real estate professionals in the US market. We’re building a best-in-class product with world-class talent to serve customers who rave about us.
Advanced englishDesign, simulate, implement and test digital logic for FPGA using VerilogPerform synthesis, timing analysis, floorplanning and test using Xilinx Vivado and Synopsys HAPS tools. Write constraints to fix timing problems.Programming skills in TCL (for Vivado and openOCD)
Ensino Superior Completo na área de Tecnologia da Informação, Estatística, Engenharias e áreas afins. Conhecimento técnico sobre métricas e indicadores de desempenho (KPIs), bem como domínio das diversas métricas de análise de mercado; Conhecimento em metodologias ágeis